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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 68: XADC Specifications (Cont’d)
Parameter
DCLK Duty Cycle
Symbol
Comments/Conditions
Min
40
Typ
–
Max
60
Units
%
XADC Reference (5)
External Reference
On-Chip Reference
V REFP
Externally supplied reference voltage
Ground V REFP pin to AGND,
T j = –40°C to 100°C
1.20
1.2375
1.25
1.25
1.30
1.2625
V
V
Notes:
1.
2.
3.
4.
5.
Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature
is enabled.
Only specified for bitstream option XADCEnhancedLinearity = ON.
For a detailed description, see the ADC chapter in the 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS
Analog-to-Digital Converter User Guide ( UG480 ).
For a detailed description, see the Timing chapter in the 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS
Analog-to-Digital Converter User Guide ( UG480 ).
Any variation in the reference voltage from the nominal V REFP = 1.25V and V REFN = 0V will result in a deviation from the ideal transfer
function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by ±4% is permitted. On-chip reference variation is ± 1%.
Configuration Switching Characteristics
Table 69: Configuration Switching Characteristics
Speed Grade
Symbol
Description
-3
1.0V
-2/-2L
-1/-1M
0.9V
-2L
Units
Power-up Timing Characteristics
T PL (1)
T POR (1)
T PROGRAM
Program latency
Power-on reset (50 ms ramp rate time)
Power-on reset (1 ms ramp rate time)
Program pulse width
5
10/50
10/35
250
5
10/50
10/35
250
5
10/50
10/35
250
5
10/50
10/35
250
ms, Max
ms, Min/Max
ms, Min/Max
ns, Min
CCLK Output (Master Mode)
T ICCK
T MCCKL
T MCCKH
F MCCK
F MCCK_START
F MCCKTOL
Master CCLK output delay
Master CCLK clock Low time duty cycle
Master CCLK clock High time duty cycle
Master CCLK frequency
Master CCLK frequency for AES encrypted x16
Master CCLK frequency at start of configuration
Frequency tolerance, master mode with respect to
nominal CCLK
150
40/60
40/60
100.00
50.00
3.00
±50
150
40/60
40/60
100.00
50.00
3.00
±50
150
40/60
40/60
100.00
50.00
3.00
±50
150
40/60
40/60
70.00
35.00
3.00
±50
ns, Min
%, Min/Max
%, Min/Max
MHz, Max
MHz, Max
MHz, Typ
%, Max
CCLK Input (Slave Modes)
T SCCKL
T SCCKH
F SCCK
Slave CCLK clock minimum Low time
Slave CCLK clock minimum High time
Slave CCLK frequency
2.50
2.50
100.00
2.50
2.50
100.00
2.50
2.50
100.00
2.50
2.50
70.00
ns, Min
ns, Min
MHz, Max
EMCCLK Input (Master Mode)
T EMCCKL
T EMCCKH
F EMCCK
External master CCLK Low time
External master CCLK High time
External master CCLK frequency
2.50
2.50
100.00
2.50
2.50
100.00
2.50
2.50
100.00
2.50
2.50
70.00
ns, Min
ns, Min
MHz, Max
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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